Difference Between Fast Ethernet And Serial Interface
Serial interfaces such as PCI Express, Serial ATA (SATA) and USB have a single specification for each of their respective data rates, but Ethernet has many different specifications for the same data rate. For example, 10GBASE-ER and 10GBASE-KR are 10 Gbps Ethernet specifications but they describe different interconnect medium interfaces.
Hi guys,So when I look at photos of Cisco routers they have 3 different ethernet ports. Here's a picture of what I'm talking about:. One says Fast Ethernet 0/0 - Does this mean fast ethernet?
100Mbps?. The second says Console - That means that the console cable that connects to a computer to access it's interface, right?. I have no idea what AUX means. Just a spare port?.
So if my home router has a WAN port and a switch. I plug the WAN connection into the WAN port and my local devices into the switch ports.Now I change to the Cisco router. My WAN connection connects to the. Erm?. My other Cisco switch connects to the. Erm?So where do I plug in the WAN connection and where do I plug in the switch?I'm really sorry it's such a newbie question but please I don't get it.
Of article:The telephone company maintains large battery systems that supply DC line voltage for the operation of analog telephone service (', or POTS) at customer locations. The voltage supplied is a compromise between operational needs for reliable service and safety precautions for customers and service personnel.
The length of the line to a customer telephone interface presents a resistance across which the central office voltage experiences a drop and therefore the voltage at the customer site may vary. The nominal value is 48V, but the central office is adjusted to between 50 and 52 volts.Interesting: Parent commenter can. Will also delete on comment score of -1 or less. To answer your questions in order:1.Yes - this means FastEthernet - 100 Mbps2.Yes - This is the console port for serial access using a rollover DB9-RJ-45 console cable.3.No - It is not 'just a spare port' The AUX port is for a back-up connection through a dial-up modem in case the primary connection fails.As for your home connections, if these are the only ports on this router, you will need to route on a stick using VLANs and sub-interfaces. If you have an additional FastEthernet or GigabitEthernet port, use this one for the router- modem connection and the other for the router- switch connection.Correct.This isn't an Ethernet port. You are correct that it's for the console cable, which you connect to a serial port (or a USB/serial adapter.) This is for configuring the router, not for routing through.Aux is another console port, which traditionally would have been connected to a modem. Again, you can't route through this port.In a home network, the concept of 'LAN' and 'WAN' make sense.
In bigger networks, they might not do - you just have networks and other networks which you connect together.On a router that's only got a single fastethernet port for routing, you would need to create subinterfaces using VLANs and connect to a switch to do anything useful. On the switch you would configure a WAN VLAN, a LAN VLAN, and a trunk port carrying both to the router and plug your LAN devices into the ports in the LAN VLAN and your WAN connection into the port in the WAN VLAN.
The media-independent interface (MII) was originally defined as a standard interface to connect a Fast Ethernet (i.e., 100 Mbit/s) media access control (MAC) block to a PHY chip. The MII is standardized by IEEE 802.3u and connects different types of PHYs to MACs. Being media independent means that different types of PHY devices for connecting to different media (i.e. twisted pair, fiber optic, etc.) can be used without redesigning or replacing the MAC hardware. Thus any MAC may be used with any PHY, independent of the network signal transmission media.
The MII can be used to connect a MAC to an external PHY using a pluggable connector, or directly to a PHY chip which is on the same PCB. On a PC the CNR connector Type B carries MII bus interface signals.
Network data on the interface is framed using the IEEE Ethernet standard. As such it consists of a preamble, start frame delimiter, Ethernet headers, protocol-specific data and a cyclic redundancy check (CRC). The original MII transfers network data using 4-bit nibbles in each direction (4 transmit data bits, 4 receive data bits). The data is clocked at 25 MHz to achieve 100 Mbit/s throughput. The original MII design has been extended to support reduced signals and increased speeds. Current variants include, reduced media-independent interface (RMII), gigabit media-independent interface (GMII), reduced gigabit media-independent interface (RGMII), serial gigabit media-independent interface (SGMII), high serial gigabit media-independent interface (HSGMII), quad serial gigabit media-independent interface (QSGMII), and 10-gigabit media-independent interface (XGMII).
The Management Data Input/Output (MDIO) serial bus is a subset of the MII that is used to transfer management information between MAC and PHY. At power up, using autonegotiation, the PHY usually adapts to whatever it is connected to unless settings are altered via the MDIO interface.
Standard MII[edit]
The standard MII features a small set of registers:[1]
- Basic Mode Configuration (#0)
- Status Word (#1)
- PHY Identification (#2, #3)
- Ability Advertisement (#4)
- Link Partner Ability (#5)
- Auto Negotiation Expansion (#6)
The MII Status Word is the most useful datum, since it may be used to detect whether an Ethernet NIC is connected to a network. It contains a bit field with the following information:[2]
| Bit value | Meaning |
|---|---|
| 0x8000 | Capable of 100BASE-T4 |
| 0x7800 | Capable of 10/100 HD/FD (most common) |
| 0x0040 | Preamble suppression permitted |
| 0x0020 | Autonegotiation complete |
| 0x0010 | Remote fault |
| 0x0008 | Capable of Autonegotiation |
| 0x0004 | Link established |
| 0x0002 | Jabber detected |
| 0x0001 | Extended MII registers exist |
Transmitter signals[edit]
| Signal name | Description | Direction |
|---|---|---|
| TX_CLK | Transmit clock | PHY to MAC |
| TXD0 | Transmit data bit 0 (transmitted first) | MAC to PHY |
| TXD1 | Transmit data bit 1 | MAC to PHY |
| TXD2 | Transmit data bit 2 | MAC to PHY |
| TXD3 | Transmit data bit 3 | MAC to PHY |
| TX_EN | Transmit enable | MAC to PHY |
| TX_ER | Transmit error (optional) | MAC to PHY |
The transmit clock is a free-running clock generated by the PHY based on the link speed (25 MHz for 100 Mbit/s, 2.5 MHz for 10 Mbit/s). The remaining transmit signals are driven by the MAC synchronously on the rising edge of TX_CLK. This arrangement allows the MAC to operate without having to be aware of the link speed. The transmit enable signal is held high during frame transmission and low when the transmitter is idle.
Transmit error may be raised for one or more clock periods during frame transmission to request the PHY to deliberately corrupt the frame in some visible way that precludes it from being received as valid. This may be used to abort a frame when some problem is detected after transmission has already started. The MAC may omit the signal if it has no use for this functionality, in which case the signal should be tied low for the PHY.
More recently, raising transmit error outside frame transmission is used to indicate the transmit data lines are being used for special-purpose signalling. Specifically, the data value 0b0001 (held continuously with TX_EN low and TX_ER high) is used to request an EEE-capable PHY to enter low power mode.
Receiver signals[edit]
| Signal name | Description | Direction |
|---|---|---|
| RX_CLK | Receive clock | PHY to MAC |
| RXD0 | Receive data bit 0 (received first) | PHY to MAC |
| RXD1 | Receive data bit 1 | PHY to MAC |
| RXD2 | Receive data bit 2 | PHY to MAC |
| RXD3 | Receive data bit 3 | PHY to MAC |
| RX_DV | Receive data valid | PHY to MAC |
| RX_ER | Receive error | PHY to MAC |
| CRS | Carrier sense | PHY to MAC |
| COL | Collision detect | PHY to MAC |
The first seven receiver signals are entirely analogous to the transmitter signals, except RX_ER is not optional and used to indicate the received signal could not be decoded to valid data. The receive clock is recovered from the incoming signal during frame reception. When no clock can be recovered (i.e. when the medium is silent), the PHY must present a free-running clock as a substitute.
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The receive data valid signal (RX_DV) is not required to go high immediately when the frame starts, but must do so in time to ensure the 'start of frame delimiter' byte is included in the received data. Some of the preamble nibbles may be lost.
Similar to transmit, raising RX_ER outside a frame is used for special signalling. For receive, two data values are defined: 0b0001 to indicate the link partner is in EEE low power mode, and 0b1110 for a false carrier indication.
The CRS and COL signals are asynchronous to the receive clock, and are only meaningful in half-duplex mode. Carrier sense is high when transmitting, receiving, or the medium is otherwise sensed as being in use. If a collision is detected, COL also goes high while the collision persists.
In addition, the MAC may weakly pull-up the COL signal, allowing the combination of COL high with CRS low (which a PHY will never produce) to serve as indication of an absent/disconnected PHY.
Management signals[edit]
| Signal name | Description | Direction |
|---|---|---|
| MDIO | Management data | Bidirectional |
| MDC | Management data clock | MAC to PHY |
MDC and MDIO constitute a synchronous serial data interface similar to I²C. As with I²C, the interface is a multidrop bus so MDC and MDIO can be shared among multiple PHYs.
Limitations[edit]
The interface requires 18 signals, out of which only two (MDIO and MDC) can be shared among multiple PHYs. This presents a problem, especially for multiport devices; for example, an eight-port switch using MII would need 8 × 16 + 2 = 130 signals.
Reduced media-independent interface[edit]
Reduced media-independent interface (RMII) is a standard which was developed to reduce the number of signals required to connect a PHY to a MAC. Reducing pin count reduces cost and complexity for network hardware especially in the context of microcontrollers with built-in MAC, FPGAs, multiport switches or repeaters, and PC motherboard chipsets. Four things were changed compared to the MII standard to achieve this. These changes mean that RMII uses about half the number of signals compared to MII.
- The two clocks TXCLK and RXCLK are replaced by a single clock. This clock is an input to the PHY rather than an output, which allows the clock signal to be shared among all PHYs in a multiport device, such as a switch.
- The clock frequency is doubled from 25 MHz to 50 MHz, while the data paths are narrowed from 4 bits to 2 bits.
- RXDV and CRS signals are multiplexed into one signal.
- The COL signal is removed.
| Signal name | Description | Direction |
|---|---|---|
| REF_CLK | Continuous 50 MHz reference clock | Reference clock may be an input on both devices from an external clock source, or may be driven from the MAC to the PHY |
| TXD0 | Transmit data bit 0 (transmitted first) | MAC to PHY |
| TXD1 | Transmit data bit 1 | MAC to PHY |
| TX_EN | When high, clock data on TXD0 and TXD1 to the transmitter | MAC to PHY |
| RXD0 | Receive data bit 0 (received first) | PHY to MAC |
| RXD1 | Receive data bit 1 | PHY to MAC |
| CRS_DV | Carrier Sense (CRS) and RX_Data Valid (RX_DV) multiplexed on alternate clock cycles. In 10 Mbit/s mode, it alternates every 10 clock cycles. | PHY to MAC |
| RX_ER | Receive error (optional on switches) | PHY to MAC |
| MDIO | Management data | Bidirectional |
| MDC | Management data clock. | MAC to PHY |
MDC and MDIO can be shared among multiple PHYs.
The receiver signals are referenced to the REF_CLK, same as the transmitter signals.
This interface requires 9 signals, versus MII's 18. Of those 9, on multiport devices, MDIO, MDC, and REF_CLK may be shared leaving 6 or 7 pins per port.
RMII requires a 50 MHz clock where MII requires a 25 MHz clock and data is clocked out two bits at a time vs 4 bits at a time for MII or 1 bit at a time for SNI (10 Mbit/s only). Data is sampled on the rising edge only (i.e. it is notdouble-pumped).
The REF_CLK operates at 50 MHz in both 100 Mbit/s mode and 10 Mbit/s mode. The transmitting side (PHY or MAC) must keep all signals valid for 10 clock cycles in 10 Mbit/s mode. The receiver (PHY or MAC) samples the input signals only every ten cycles in 10 Mbit/s mode.
Limitations[edit]
There is no signal which defines whether the interface is in full or half duplex mode, but both the MAC and the PHY need to agree. This must instead be communicated over the serial MDIO/MDC interface. There is also no signal which defines whether the interface is in 10 or 100 Mbit/s mode, so this must also be handled using the MDIO/MDC interface. Version 1.2 of the RMII Consortium specification states that its MDIO/MDC interface is identical to that specified for MII in IEEE 802.3u. Current revisions of IEEE 802.3 specify a standard MDIO/MDC mechanism for negotiating and configuring the link's speed and duplex mode, but it is possible that older PHY devices might have been designed against obsolete versions of the standard, and may therefore use proprietary methods to set speed and duplex.
The lack of the RX_ER signal which is not connected on some MACs (such as multiport switches) is dealt with by data replacement on some PHYs to invalidate the CRC. The missing COL signal is derived from AND-ing together the TX_EN and the decoded CRS signal from the CRS_DV line in half duplex mode. This means a slight modification of the definition of CRS: On MII, CRS is asserted for both Rx and Tx frames; on RMII only for Rx frames. This has the consequence that on RMII the two error conditions no carrier and lost carrier cannot be detected, and it is difficult or impossible to support shared media such as 10BASE2 or 10BASE5.
Since the RMII standard neglected to stipulate that TX_EN should only be sampled on alternate clock cycles, it is not symmetric with CRS_DV and two RMII PHY devices cannot be connected back to back to form a repeater; this is possible, however, with the National DP83848 which supplies the decoded RX_DV as a supplemental signal in RMII mode.[3]
Signal levels[edit]
TTL logic levels are used for 5 V or 3.3 V logic. Input high threshold is 2.0 V and low is 0.8 V. The specification states that inputs should be 5 V tolerant, however, some popular chips with RMII interfaces are not 5 V tolerant. Newer devices may support 2.5 V and 1.8 V logic.
The RMII signals are treated as lumped signals rather than transmission lines. However, the IEEE version of the related MII standard specifies 68 Ω trace impedance.[4] National recommends running 50 Ω traces with 33 Ωseries termination resistors for either MII or RMII mode to reduce reflections.[citation needed] National also suggests that traces be kept under 0.15 m long and matched within 0.05 m on length to minimize skew.[4]:5
Gigabit media-independent interface[edit]
The gigabit media-independent Interface (GMII) is an interface between the medium access control (MAC) device and the physical layer (PHY). The interface operates at speeds up to 1000 Mbit/s, implemented using a data interface clocked at 125 MHz with separate eight-bit data paths for receive and transmit, and is backwards compatible with the MII specification and can operate on fall-back speeds of 10 or 100 Mbit/s.
The GMII interface was first defined for 1000BASE-X in IEEE 802.3z-1998 as clause 35, and subsequently incorporated into IEEE 802.3-2000 onwards.[5]
Transmitter signals[edit]
| Signal name | Description |
|---|---|
| GTXCLK | Clock signal for gigabit TX signals (125 MHz) |
| TXCLK | Clock signal for 10/100 Mbit/s signals |
| TXD[7.0] | Data to be transmitted |
| TXEN | Transmitter enable |
| TXER | Transmitter error (used to intentionally corrupt a packet, if necessary) |
There are two transmitter clocks. The clock used depends on whether the PHY is operating at gigabit or 10/100 Mbit/s speeds. For gigabit operation, the GTXCLK is supplied to the PHY and the TXD, TXEN, TXER signals are synchronized to this. for 10 or 100 Mbit/s operation, the TXCLK is supplied by the PHY and is used for synchronizing those signals. This operates at either 25 MHz for 100 Mbit/s or 2.5 MHz for 10 Mbit/s connections. In contrast, the receiver uses a single clock signal recovered from the incoming data.
Receiver signals[edit]
| Signal name | Description |
|---|---|
| RXCLK | Received clock signal (recovered from incoming received data) |
| RXD[7.0] | Received data |
| RXDV | Signifies data received is valid |
| RXER | Signifies data received has errors |
| COL | Collision detect (half-duplex connections only) |
| CS | Carrier sense (half-duplex connections only) |
Management signals[edit]
| Signal name | Description |
|---|---|
| MDC | Management interface clock |
| MDIO | Management interface I/O bidirectional pin. |
The management interface controls the behavior of the PHY. There are 32 addresses, each containing 16 bits. The first 16 addresses have a defined usage,[6] while the others are device specific. These registers can be used to configure the device (say 'only gigabit, full duplex', or 'only full duplex') or can be used to determine the current operating mode.
Reduced gigabit media-independent interface[edit]
| [Mbit/s] | [MHz] | Bits/clock cycle |
|---|---|---|
| 10 | 2.5 | 4 |
| 100 | 25 | 4 |
| 1000 | 125 | 8 |
Reduced gigabit media-independent interface (RGMII) specifies a particular interface between an Ethernet MAC and PHY.
RGMII uses half the number of data pins as used in the GMII interface. This reduction is achieved by clocking data on both the rising and falling edges of the clock in 1000 Mbit/s operation, and by eliminating non-essential signals (carrier-sense and collision-indication). Thus RGMII consists only of: RX_CTL, RXC, RXD[3:0], TX_CTL, TXC, TXD[3:0] (12 pins, as opposed to GMII's 24).
Unlike GMII, the transmit clock signal is always provided by the MAC on the TXC line, rather than being provided by the PHY for 10/100 Mbit/s operation and by the MAC at 1000 Mbit/s. Source-synchronous clocking is used: the clock signal that is output (by either the PHY or the MAC) is synchronous with the data signals. This requires the PCB to be designed to add a 1.5–2 ns delay to the clock signal to meet the setup and hold times on the sink. RGMII v2.0 specifies an optional internal delay, obviating the need for the PCB designer to add delay; this is known as RGMII-ID.
To achieve these. Archived from the original on 2017-02-05. Retrieved 2018-11-19.
External links[edit]
- Serial-GMII Specification Revision 1.7 (ENG-46158)(PDF), archived from the original(PDF) on 2015-07-14
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